In microelectronics products, transistors and other devices are typically fabricated and interconnected to form an integrated circuit. The performance of the integrated circuit is often directly related to the performance of the fabricated transistors. In some proposed processes, the transistors are three dimensional transistors having fins with two (dual or double gate transistors) or three (tri-gate transistors) channel surfaces in contact with the gate structure. Three dimensional transistors can be contrasted with planar transistors, which have one channel surface in contact with the gate structure. Due to the greater surface area of contact between the channel region and the gate structure, three dimensional transistors offer the potential for performance advantages over planar transistors.
Further, processing of transistors (three dimensional or planar) has traditionally involved the use of monocrystalline silicon for the channel material, silicon dioxide for the gate dielectric, and polysilicon for the gate electrode. However, the continued scaling to smaller and smaller transistors, along with a desire for increased performance, has driven the transition to high-k gate dielectrics (those having a dielectric constant, k, greater than that of silicon dioxide, i.e., greater than about 4), which offer greater capacitance and less leakage. The move to high-k gate dielectrics has also enabled new gate electrode materials, such as metal gate electrodes, to provide advantageous work function materials in the gate electrode.
In some processes, fabricating a three dimensional transistor includes forming a dielectric layer and an electrode layer over the transistor fin. The dielectric and electrode layers are then patterned and etched to expose portions of the fin. In such processes, etching the fins has numerous difficulties. For example, it may be difficult to remove all of the materials from the sidewalls of the fins, particularly with high-k dielectrics and metal electrodes. In some instances, etching the dielectric and electrode layers to expose the sidewalls of the fins can erode the fin causing non-operative devices and low yields.